As is now evident, that advice was mis-guided.
Just as there are markets for a variety of processor chips, there also are emerging markets for a variety of memory devices. Some memory devices will incur a cost penalty in order to provide lower latency or lower energy. For example, see the slide below that was presented by Hynix at an ISCA 2016 keynote, arguing for a memory chip that offers 30% lower latency, while incurring a 28% area overhead.
|From the ISCA 2016 keynote talk by Seok-Hee Lee (SK Hynix)|
Hopefully, program committees will no longer cite the "cost-sensitive memory industry" to reject otherwise good papers. Market forces are constantly evolving -- they should ideally not come in the way of a strong technical argument.